Memory and logic devices are typically provided as internal, semiconductor, integrated circuits in computers and many other electronic devices including handheld devices such as cellular telephones and personal digital assistants. There are many different types of memory including static random-access memory (SRAM), read only memory (ROM), flash memory, dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM) that are functionally integrated with logic devices such as microprocessors, microcontrollers, digital signal processors, programmable logic devices, wireless communication, and networking.
Many current and future devices require increasing integration of logic and memory functions within the same integrated circuit technology. Current microprocessors, for example, embed ROM and SRAM arrays with logic libraries, logic device (e.g., ALU), and logic circuits to achieve desired device functionality within the same chip. A basic building block for a logic cell is a CMOS inverter that consists of a pair of PMOS and NMOS transistors integrated to have common input and output nodes between power supply (VDD) and ground potentials. As the size of a unit transistor shrinks with scaling, large arrays of memories including DRAMs are being integrated into logic devices to achieve powerful functions.
Conventional DRAM cells are comprised of a switching transistor and an integrated storage capacitor tied to the storage node of the transistor. Charge storage is enhanced by providing appropriate storage capacity in the form of a stacked capacitor or a trench capacitor in parallel with the depletion capacitance of the floating storage node. DRAM cells are volatile and therefore lose data when the power is removed. Additionally, due to leakage, the capacitor must be refreshed periodically to maintain the charge.
As computers and other devices mentioned above become smaller and their performance increases, the computer memories have also gone through a corresponding size reduction and performance increase. For example, DRAM cells, typically comprised of silicon IC technology, has been progressively scaled in feature size from the nearly 2000 nm node technology of prior years to the current 100 nm node technology.
During this period, power supply voltages have been scaled from nearly 8 volts to the approximately 2 volts that is presently used. The gate insulator, primarily SiO2, has had an effective oxide thickness (EOT) that has been scaled from 50 nm to approximately 5 nm at the present time. At thicknesses below 5 nm, leakage through the oxide becomes appreciable thus providing constraints and challenges towards further scalability from the standpoint of power, speed, and circuit reliability. This is especially true for dynamic circuits.
Aside from oxide integrity and reliability, transistor design for deep sub-micron channel length (i.e., L<200 nm) requires critical control of thermal budget to achieve control of short channel effect, performance, and reliability. Integration of embedded DRAM below 100 nm node has been a challenge not only due to capacitor scalability concerns of DRAM cells but also because of the requirement for higher thermal budgets to achieve leakage, yield, and density objectives of the embedded DRAM cells.
Recently, embedded non-volatile memory (NVM) technology has been gaining considerable attention due to the potential of low power and hand-held device applications. It would be desirable to have the non-volatile flash memory attributes in a cell that has DRAM performance. However, conventional floating gate flash memory technology has not been scalable in power supply voltage levels, consumes higher than desired power during programming, and also requires high programming voltages (e.g., 10-20V for the 100 nm technology node). Embedding such a device requires on-chip generation of the high voltages and routing these voltages in an otherwise scaled low voltage logic technology adds considerable process complexity and cost and compromises functionality.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a more scalable, low power, high performance integrated logic memory that would provide high performance logic and non-volatile memory at lower power.